Qualifications :- Bachelor's Degree, Master in Electrical Engineering or relevant field
Other Requirements :
- Preferable with experience of 3 years and above in technical areas
- Experience in front-end physical implementation, front-end integration, or physical verification
- Knowledgeable in all aspects of ASIC design flow
- Familiar with FEINT EDA tools
- Synthesize experience by DC/DC-NXT/Fusion-Compiler
- EQV debug experience by FM/LEC
- Low power check experience by VC-LP
- Static Timing Analysis experience by PT
- Power Analysis experience by PTPX
- Good at scripts like Python/Perl/Tcl/Shell
- Good leadership skills and teamwork
- Good training skills to ramp-up new team members
- Perform working assignment for team members, tracking and supporting for critical problems
- Co-work with IP/DFT/PD team to improve timing/area/power during synthesize
- Netlist quality check including EQV/LowPower/Timing
- Generate full-chip level SDC and SDC quality check
Job Type: Contract
Contract length: 12 months
Pay: RM8,
- 00 - RM10,000.00 per month
Schedule:
Monday to Friday
