Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)

Develop SI and PI design for server/storage/communication products. Major works are to serve

as the signal integrity analyst and designer provides the support to internal team, suppliers, and

customers to deliver the new products.

Job Responsibilities:

PCB material choosing and stack-up definition.

3D passive channel modeling, perform SerDes channel extraction using electromagnetic tools.

Perform signal integrity pre-layout and post-layout analysis in R&D phase.

Perform static timing and signal integrity analysis of parallel (common clock, source-

synchronous) interfaces.

Design and analysis of multi-gigabit serial links, including lab verification and tuning.

Perform power integrity analysis on power delivery network.

Generate and verify PCB layout rules, manage constraints for PCB layout.

Work directly with ASIC and PCB design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability.

Cooperate with R&D team and signal test engineers on debugging, failure analysis and fixing issues discovered during test.

Be familiar with SAS, PCIe, DDR3/4, 25G/56G Ethernet specification is a plus.

Job Requirement:

Experience with at least one PCB post-route SI tool: Cadence SPECCTRAQuest, Mentor ICX, SiSoft SI-Auditor (preferred), Sigrity Power SI.

Experience with Synopsys HSPICE and/or Keysight ADS for both time and frequency domain circuit simulation.

Experience with at least one 3-D field solver (CST Microwave Studio, ANSYS HFSS).

Experience with TDR and VNA measurements.

Proficiency in Electromagnetic, Transmission-line & S-parameters theory and modeling.

Good understanding on power distribution and SerDes design.

BSEE/ MSEE or related field with applicable work experience.

Experience of script languages like VB, Perl or Python.

Use of mathematic tools like Matlab.

Strong written and oral communication in English with customer service skills.