Hardware Optimization Engineer - AI Training Systems

Early Applicant

Exp: 3-5 Years

Job Description

Job Overview

We are seeking an exceptional Hardware Design Developer to join our team and play a crucial role in
leveraging hardware design platforms to generate training data for enhancing enterprise LLMs (Large
Language Models) capabilities. This is a unique opportunity to directly contribute to the advancement
of enterprise LLMs, ensuring they perform with outstanding efficiency and intelligence. As a Hardware
Design Developer, you will work closely with research teams to configure, develop, and optimise
hardware design solutions tailored for LLM training and benchmarking.

Education & Experience

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related
field.
3-5 years of proven experience in hardware design development.
Expertise in Hardware Description Languages (HDLs) such as Verilog, SystemVerilog, VHDL,
and SystemC.
Proficiency in scripting, front-end workflows, and verification within the hardware design
environment.
Experience with Synopsys/Cadence or open-source toolchains is highly preferred.

Key Responsibilities

Develop, configure, and customize hardware design platforms to generate essential training
data for enterprise LLMs.
Collaborate with research teams to translate requirements into actionable data insights,
directly influencing LLMs performance and capability enhancement.
Uphold best practices in coding, debugging, and documentation to ensure hardware design
solutions are optimized for LLM training and benchmarking processes.
Work with cross-functional teams to identify and prioritize key needs, contributing to the LLMs
ability to understand and automate complex workflows.
Continuously refine and improve hardware design processes to enhance efficiency and
integration within the LLM training ecosystem.

Requirements

Strong proficiency in Hardware Description Languages (Verilog, SystemVerilog, VHDL,
SystemC).
Expertise in hardware design environments, scripting, and front-end workflows.
Experience in verification workflows and integrations within hardware design platforms.
Excellent problem-solving, communication, and collaboration skills.
Familiarity with leading toolchains such as Synopsys or Cadence.

Preferred Qualifications

Expertise in Universal Verification Methodology (UVM) environments.
Experience with Formal Verification, Assertion Coding, and SystemVerilog Assertions (SVA).
Strong understanding of Lint processes and refinement.
Background in Computer Architecture and Assembly Coding/Debugging.
Familiarity with Machine Learning (ML) and Artificial Intelligence (AI) systems is a plus.